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9121d-indco-09/14 features frequency receiving range of (3 versions) f 0 = 312.5mhz to 317.5mhz or f 0 = 431.5mhz to 436.5mhz or f 0 = 868mhz to 870mhz 30db image rejection receiving bandwidth b if = 300khz for 315mhz/433mhz version b if = 600khz for 868mhz version fully integrated lc-vco and pll loop filter very high sensitivity with power matched lna atmel ? ata8203/ata8204: ?107dbm, fsk, br_0 (1.0kbit/s to 1.8kbit/s), manchester, ber 10e-3 ?113dbm, ask, br_0 (1.0kbit/s to 1. 8kbit/s), manchester, ber 10e-3 atmel ata8205: ?105dbm, fsk, br_0 (1.0kbit/s to 1.8kbit/s), manchester, ber 10e-3 ?111dbm, ask, br_0 (1.0kbit/s to 1.8kbit/s), manchester, ber 10e-3 high system iip3 ?18dbm at 868mhz ?23dbm at 433mhz ?24dbm at 315mhz system 1-db compression point ?27.7dbm at 868mhz ?32.7dbm at 433mhz ?33.7dbm at 315mhz high large-signal capability at gsm band (blocking ?33dbm at +10mhz, iip3 = ?24dbm at +20mhz) logarithmic rssi output xto start-up with negative resistor of 1.5k 5v to 20v automotive compatible data interface data clock available for manchester and bi-phase-coded signals programmable digital noise suppression low power consumption due to configurable polling ata8203/ata8204/ata8205 industrial uhf ask/fsk receiver datasheet
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 2 temperature range ?40c to +85c esd protection 2kv hbm, all pins communication to microcontroller possibl e using a single bi-directional data line low-cost solution due to high integration level with minimum external circuitry requirements supply voltage range 4.5v to 5.5v benefits low bom list due to high integration use of low-cost 13mhz crystal lowest average current consumption for application due to self polling feature reuse of atmel ata5743 software world-wide coverage with one pcb due to 3 versions are pin compatible
3 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 1. description the atmel ? ata8203/ata8204/ata8205 is a multi-chip pll receiv er device supplied in an sso20 package. it has been specially developed for the demands of rf low-cost data transmission systems with data rates from 1kbit/s to 10kbit/s in manchester or bi-phase code. its main applic ations are in the areas of aftermarket keyless entry systems, and tire pressure monitoring systems, telemetering, cons umer/industrial remote control applicatio ns, home entertainment, access control systems, and security technology s ystems. it can be used in the frequency receiving range of f 0 = 312.5mhz to 317.5mhz, f 0 = 431.5mhz to 436.5mhz or f 0 = 868mhz to 870mhz for ask or fsk data transmission. all the statements made below refer to 315mhz, 433mhz and 868.3mhz applications. figure 1-1. system block diagram micro- controller pll uhf ask/fsk remote control receiver uhf ask/fsk remote control transmitter ata8401/02/03/04/05 ata8203/ ata8204/ ata8205 lna vco pll xto power amp. vco antenna demod. if amp control 1 to 5 xto antenna
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 4 figure 1-2. block diagram 4. order f 0 = 1 mhz if amp. f :2 or :4 f :2 or :3 polling circuit and control logic standby logic data interface sensitivity reduction loop filter f :128 or :64 if amp. fsk/ask demodulator and data filter rssi limiter out dem_out xto lna clk polling/_on ic_active xtal1 xtal2 mode data_clk data fe rssi poly-lpf f g = 7 mhz lpf f g = 2.2 mhz cdem lnaref lnagnd lna_in dvcc dgnd agnd avcc sens rssi lc-vco
5 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 2. pin configuration figure 2-1. pinning sso20 test1 rssi lna_in lnagnd agnd lnaref sens ic_active cdem avcc ata8203/ ata8204/ ata8205 5 6 9 10 7 8 1 2 3 4 mode dvcc test3 test2 xtal2 xtal1 data polling/_on dgnd data_clk 16 15 12 11 14 13 20 19 18 17 table 2-1. pin description pin symbol function 1 sens sensitivity-control resistor 2 ic_active ic condition indicator: low = sleep mode, high = active mode 3 cdem lower cut-off frequency data filter 4 avcc analog power supply 5 test 1 test pin, during operation at gnd 6 rssi rssi output 7 agnd analog ground 8 lnaref high-frequency reference node lna and mixer 9 lna_in rf input 10 lnagnd dc ground lna and mixer 11 test 2 do not connect during operating 12 test 3 test pin, during operation at gnd 13 xtal1 crystal oscillator xtal connection 1 14 xtal2 crystal oscillator xtal connection 2 15 dvcc digital power supply 16 mode selecting 315mhz/other versions low: 315mhz version (atmel ata8203) high: 433mhz/868mhz versions (atmel ata8204/ata8205) 17 data_clk bit clock of data stream 18 dgnd digital ground 19 polling/_on selects polling or receiving mode; low: receiving mode, high: polling mode 20 data data output/configuration input
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 6 3. rf front-end the rf front-end of the receiver is a low- if heterodyne configuration t hat converts the input signal into about 1mhz if signal with a typical image rejection of 30db. according to figure figure 1-2 on page 4 the front-end consists of an lna (low noise amplifier), lo (local oscillat or), i/q mixer, polyphase low-pass filter and an if amplifier. the pll generates the drive frequency f lo for the mixer using a fully integrated synthesizer with integrated low noise lc- vco (voltage controlled oscillator) and pll-loop filter. the xto (crystal oscill ator) generates the reference frequency f ref =f xto /2 (868mhz and 433mhz versions) or f ref =f xto /3 (315mhz version). the integrated lc-vco generates two or four times the mixer drive frequency f vco . the i/q signals for the mixer are generated with a divide by two or four circuit (f lo =f vco /2 for 868mhz version, f lo =f vco /4 for 433mhz and 315mhz versions). f vco is divided by a factor of 128 or 64 and feeds into a phase frequency detector and is compared with f ref . the output of the phase frequ ency detector is fed into an integrated loop filter and thereby generates the contro l voltage for the vco. if f lo is determined, f xto can be calculated using the following formula: f ref =f lo /128 for 868mhz band, f ref =f lo /64 for 433mhz bands, f ref =f lo /64 for 315mhz bands. the xto is a two-pin oscillator that operates at the series re sonance of the quartz crystal with high current but low voltage signal, so that there is only a small vo ltage at the crystal oscillator frequency at pins xtal1 and xtal2. according to figure 3-1 , the crystal should be connect ed to gnd with two capacitors c l1 and c l2 from xtal1 and xtal2 respectively. the value of these capacitors are reco mmended by the crystal supplier. due to an inductive impedance at steady state oscillation and some pcb parasitics, a lower value of c l1 and c l2 is normally necessary. the value of c lx should be optimized for the individual board layout to achieve the exact value of f xto and hence of f lo . (the best way is to use a crystal with known load resonance frequency to find the right value for this capacitor.) when designing the system in terms of receiving bandwidth and local oscillator accuracy, the accuracy of the crystal and the xto must be considered. figure 3-1. xto peripherals the nominal frequency f lo is determined by the rf input frequency f rf and the if frequency f if using the following formula (low-side injection): f lo = f rf ? f if to determine f lo , the construction of the if filter must be considered. the nominal if frequency is f if = 950khz. to achieve a good accuracy of the filter corner frequencies, the filter is tuned by the crystal frequency f xto . this means that there is a fixed relationship between f if and f lo . f if = f lo /318 for the 315mhz band (atmel ? ata8203) f if = f lo /438 for the 433.92mhz band (atmel ata8204) f if = f lo /915 for the 868.3mhz band (atmel ata8205) the relationship is designed to achieve the nominal if frequency of: f if = 987hz for the 315mhz and b if = 300khz (atmel ata8203) f if = 987khz for the 433.92mhz and b if = 300khz (atmel ata8204) f if = 947.8khz for the 868.3mhz and b if = 600khz (atmel ata8205) the rf input either from an antenna or from an rf generato r must be transformed to the rf input pin lna_in. the input impedance of this pin is provided in the electrical paramete rs. the parasitic board inductanc es and capacitances influence the input matching. the rf receiver atmel ata8203/ata8204/a ta8205 exhibits its highest sens itivity if the lna is power matched. because of this, matching to a saw filter, a 50 or an antenna is easier. figure 14-1 on page 30 ?application circuit? shows a typi cal input matching network for f rf = 315mhz, f rf = 433.92mhz or f rf = 868.3mhz to 50 . the input matching network shown in table 14-2 on page 30 is the reference network for the parameters given in the electrical characteristics. xtal2 test2 test3 xtal1 dvcc v s c l2 c l1
7 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 4. analog signal processing 4.1 if filter the signals coming from the rf front-end are filtered by the fu lly integrated 4th-order if filter . the if center frequency is: f if = 987khz for the 315 mhz and b if = 300khz (atmel ? ata8203) f if = 987khz for the 433.92 mhz and b if = 300khz (atmel ata8204) f if = 947.9khz for the 868.3 mhz and b if = 600khz (atmel ata8205) the nominal bandwidth is 300 khz for ata8203 and ata8204 and 600 khz for ata8205. 4.2 limiting rssi amplifier the subsequent rssi amplifier enhances the output signal of t he if amplifier before it is fed into the demodulator. the dynamic range of this amplifier is r rssi = 60db. if the rssi amplifier is operated within its linear range, the best s/n ratio is maintained in ask mode. if the dynamic range is exceeded by the transmitter signal, the s/n ratio is defined by the ratio of the maximum rssi output voltage and the r ssi output voltage due to a disturber. the dynamic range of the rssi amplifier is exceeded if the rf input signal is approximately 60 db hi gher compared to the rf input signal at full sensitivity. the s/n ratio is not affected by the dyna mic range of the rssi amplifier in fsk mode because only the hard limited signal from a high-gain limiting amplif ier is used by the demodulator. the output voltage of the rssi amplifier (v rssi) is available at pin rssi. using th e rssi output signal, the signal strength of different transmitters can be disti nguished. the usable input power range p ref is ?100dbm to ?55dbm. figure 4-1. rssi characteristics atmel ata8204 the output voltage of the rssi amplifier is internally compared to a threshold voltage v th_red . v th_red is determined by the value of the external resistor r sens . r sens is connected between pin sens and gnd or v s . the output of the comparator is fed into the digital control logic. by this means, it is possible to operate the rece iver at a lower sensitivity. if r sens is connected to gnd, the rece iver switches to full sensitivity. it is also possible to connect the pin sens directly to gnd to get the maximum sensitivity. if r sens is connected to v s , the receiver operates at a lower sensitivity. th e reduced sensitivity is defined by the value of r sens , and the maximum sensitivity is defined by the signal-to-no ise ratio of the lna input. the reduced sensitivity depends on the signal strength at the output of the rssi amplifier. since different rf input networks may exhibit slightly different values for the lna gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. this matching is described and illustrated in section 14. ?data interface? on page 30 . pin (dbm) -120 -110 -100 -90 -80 -70 -60 -50 -40 1 1.5 2 2.5 3 3.5 4.5v -40c 5.0v -40c 5.5v -40c 4.5v 25c 5.0v 25c 5.5v 25c 4.5v 85c 5.0v 85c 5.5v 85c v_rssi (v) rssi characteristics
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 8 r sens can be connected to v s or gnd using a microcontroller. the receiver can be switched from full sensitivity to reduced sensitivity or vice versa at any time. in polling mode, the receiv er does not wake up if the rf input signal does not exceed the selected sensitivity. if the receiver is already active, t he data stream at pin data disappears when the input signal is lower than defined by the reduced sensitivity. instead of the data stream, the pattern according to figure 4-2 ?steady l state limited data output pattern? is issued at pin data to indicate that the receiv er is still active (see figure 13-2 on page 28 ?data interface?). figure 4-2. steady l state li mited data output pattern 4.3 fsk/ask demodulator and data filter the signal coming from the rssi amplifier is converted into the raw data signal by the ask/ fsk demodulator. the operating mode of the demodulator is set using the bit ask/_fsk in the opmode register. logic l sets the demodulator to fsk, applying h to ask mode. in ask mode an automatic threshold control circuit (atc) is employed to set the detection reference voltage to a value where a good signal to noise ratio is achieved. this circuit also implements the effective suppression of any kind of in-band noise signals or competing transmitters. if the s/n (ratio to suppress in-band noise signals) exceeds about 10db the data signal can be detected properly. however, better values ar e found for many modulation schemes of the competing transmitter. the fsk demodulator is intended to be used for an fsk deviation of 10khz f 100khz. the data signal in fsk mode can be detected if the s/n (ratio to suppres s in-band noise signals) exceeds about 2db. this value is valid for all modulation schemes of a disturber signal. the output signal of the demodulator is f iltered by the data filt er before it is fed into the digital signal processing circuit . the data filter improves the s/n ratio as its pass-band can be adopted to the c haracteristics of the data signal. the data filter consists of a 1 st order high-pass and a 2 nd order low-pass filter. the high-pass filter cut-off frequency is defined by an extern al capacitor connected to pin cdem. the cut-off frequency of the high-pass filter is defined by the following formula: in self-polling mode the data filter must settle very rapidly to achieve a low current consumpt ion. therefore, cdem cannot be increased to very high values if self-polling is used. on the other hand, cdem must be large enough to meet the data filter requirements according to the data signal. recommended values for cdem are given in the electrical characteristics. the cut-off frequency of the low-pass filter is defined by the selected baud-rate range (br_range). the br_range is defined in the opmode register (refer to section 11. ?configuring the receiver? on page 23 ). the br_range must be set in accordance to the baud-rate used. the atmel ? ata8203/ata8204/ata8205 is designed to operate with da ta coding where the dc level of the data signal is 50%. this is valid for manchester and bi-phase coding. if other modulation schemes are used, the dc level should always remain within the range of v dc_min = 33% and v dc_max = 66%. the sensitivity may be reduce d by up to 2db in that condition. each br_range is also defined by a minimum and a maximum edge-to-edge time (t ee_sig ). these limits are defined in the electrical characteristics. they should not be exc eeded to maintain full sensitivity of the receiver. t data_l_max t data_min data fcu_df 1 2 30 k cdem --------------------------------------------------------- - =
9 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 5. receiving characteristics the rf receiver atmel ? ata8203/ata8204/ata8205 can be operated with and without a saw front-end filter. in a typical automotive application, a saw filt er is used to achieve better selectivity and large signal capability. the receiving frequency response without a saw front-e nd filter is illustrated in figure 5-1 ?narrow band receiving frequency response ata8204?. this example relates to ask mode. fsk mode exhibits a similar behavio r. the plots are printed re latively to the maximum sensitivity. if a saw filter is used, an insertion loss of about 3db must be c onsidered, but the overall selectivity is much better. when designing the system in terms of rece iving bandwidth, the lo deviation must be considered as it al so determines the if center frequency. the total lo deviation is calculated, to be the sum of the deviation of the crystal and the xto deviation of the atmel ata8203/ata8204/ata8205. low-cost crystals are specif ied to be within 90ppm ov er tolerance, temperature, and aging. the xto deviation of the atmel ata8203/ata8204/ ata8205 is an additional deviation due to the xto circuit. this deviation is specified to be 10ppm worst case for a crystal with cm = 7ff. if a crystal of 90ppm is used, the total deviation is 100ppm in that case. note t hat the receiving bandwidth and the if-filt er bandwidth are equivalent in ask mode but not in fsk mode. figure 5-1. narrow band receiving frequency response ata8204 6. polling circuit and control logic the receiver is designed to consume less than 1 ma while bein g sensitive to signals from a corresponding transmitter. this is achieved using the polling circuit. this circuit enables the signal path periodically for a short time. during this time the bit- check logic verifies the presence of a valid transmitter signal. only if a valid signal is detected, the receiver remains activ e and transfers the data to the conne cted microcontroller. if there is no valid signal present, the receiver is in sleep mode mos t of the time resulting in low current consumption. this c ondition is called polling mode. a connected microcontroller is disabled during that time. all relevant parameters of the polling logic can be configured by the connected microcontroller . this flexibility enables the user to meet the specifications in terms of current consumption, system response time, data rate etc. the receiver is very flexible with regards to the number of c onnection wires to the microcontrolle r. it can be either operated by a single bi-directional line to save ports to the connected mi crocontroller or it can be operated by up to five uni-directio nal ports. (mhz) 430 431 432 433 434 435 436 437 438 4.5v -40c 5.0v -40c 5.5v -40c 4.5v 25c 5.0v 25c 5.5v 25c -40 -30 -20 -70 -60 -50 -10 0 10 (db) image rejection versus rf frequency
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 10 7. basic clock cycle of the digital circuitry the complete timing of the di gital circuitry and the analog filtering is derived from one clock. this clock cycle t clk is derived from the crystal oscillator (xto) in combination wit h a divide by 28 or 30 circuit. according to section 3. ?rf front-end? on page 6 , the frequency of the crystal oscillator (f xto ) is defined by the rf input signal (f rfin ) which also defines the operating frequency of the local oscillator (f lo ). the basic clock cycle for atmel ? ata8204 and atmel ata8205 is t clk 28/f xto giving t clk = 2.066s for f rf = 868.3mhz and t clk = 2.069s for f rf = 433.92mhz. for atmel ata8203 the basic clock cycle is t clk =30/f ref giving t clk = 2.0382s for f rf = 315mhz. t clk controls the following application-relevant parameters: timing of the polling circuit including bit check timing of the analog and digital signal processing timing of the register programming frequency of the reset marker if filter center frequency (fif0) most applications are dominated by three transmission frequencies: f transmit = 315mhz is mainly used in usa, f transmit = 868.3mhz and 433.92mhz in europe. all timings are based on t clk . for the aforementioned frequencies, t clk is given as: application 315mhz band (f xto = 14.71875mhz, f lo = 314.13mhz, t clk = 2.0382s) application 868.3mhz band (f xto = 13.55234mhz, f lo = 867.35mhz, t clk = 2.066s) application 433.92mhz band (f xto = 13.52875mhz, f lo = 432.93mhz, t clk = 2.0696s) for calculation of t clk for applications using other fr equency bands, see table in section 18. ?electrical characteristics atmel ata8204, ata8205? on page 35 . the clock cycle of some function blocks depends on the selected baud-rate range (br_range), which is defined in the opmode register. this clock cycle t xclk is defined by the following formulas: br_range = br_range0: t xclk = 8 t clk br_range1: t xclk = 4 t clk br_range2: t xclk = 2 t clk br_range3: t xclk = 1 t clk
11 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 8. polling mode according to figure 8-1 on page 12 , the receiver stays in polling mode in a co ntinuous cycle of three different modes. in sleep mode the signal processing circuitry is disabled for the time period t sleep while consuming low current of i s =i soff . during the start-up period, t startup , all signal processing circuits are enabled and settled. in the following bit-check mode, the incoming data stream is analyzed bit-by-bit and compared with a valid transmitter signal. if no valid signal is present, the receiver is set back to sleep mode after the period t bit-check . this period varies according to each check as it is a statistical process. an average value for t bitcheck is given in the electrical characteristics. during t startup and t bit-check , the current consumption is i s =i son . the condition of the receiver is indicated on pi n ic_active. the average current consumption in polling mode is dependent on the duty cycle of the active mode and can be calculated as: during t sleep and t startup , the receiver is not sensitive to a transmitter signal. to guarantee the reception of a transmitted command, the transmitter must start the telegram with an adequate preburst. the required length of the preburst depends on the polling parameters t sleep , t startup , t bit-check and the start-up time of a connected microcontroller, t start_microcontroller . thus, t bit-check depends on the actual bit rate and the number of bits (n bit-check ) to be tested. the following formula indicates how to calculate the preburst length. t preburst t sleep + t startup + t bit-check + t start_microcontroller 8.1 sleep mode the length of period t sleep is defined by the 5-bit word sleep of t he opmode register, the extension factor x sleep (according to table 11-8 on page 25 ), and the basic clock cycle t clk . it is calculated to be: t sleep =sleep x sleep 1024 t clk the maximum value of t sleep is about 60 ms if x sleep is set to 1. the time resolution is about 2 ms in that case. the sleep time can be extended to almost half a second by setting x sleep to 8. x sleep can be set to 8 by bit x sleepstd to ?1?. setting the configuration word sleep to its maximal value put s the receiver into a permanent sleep mode. the receiver remains in this state until another value for sleep is programme d into the opmode register. this is particularily useful when several devices share a single data line. (it can also be us ed for microcontroller polling: using pin polling/_on, the receiver can be switched on and off.) i spoll i soff t sleep i son t startup t bit-check + () + t sleep t startup t bit-check ++ -------------------------------------------------------------------------------------------------------- - =
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 12 figure 8-1. polling mode flow chart 8.2 bit-check mode in bit-check mode the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. this is done by subseq uent time frame checks where the distances between 2 signal edges are continuously compared to a programmable time window. the maximum number of these edge-to-edge tests, before the receiver switches to rece iving mode, is also programmable. bit-check mode: the incoming data stream is analyzed. if the timing indicates a valid transmitter signal, the receiver is set to receiving mode. otherwise it is set to sleep mode. output level on pin ic_active = > high t bit-check i s = i son start-up mode: the signal processing circuits are enabled. after the start-up time (t startup ) all circuits are in stable condition and ready to receive. output level on pin ic_active = > high t startup i s = i son receiving mode: the receiver is turned on permanently and passes the data stream to the connected microcontroller. it can be set to sleep mode through an off command via pin data or polling/_on. output level on pin ic_active = > high i s = i son sleep mode: all circuits for signal processing are disabled. only xto and polling logic are enabled. output level on pin ic_active = > low t sleep = sleep x x sleep x 1024 x t clk i s = i soff bit check ok ? 5-bit word defined by sleep 0 to sleep 4 in opmode register sleep: is defined by the selected baud rate range and tclk. the baud-rate range is defined by baud 0 and baud 1 in the opmode register. t startup : basic clock cycle defined by f xto and pin mode t clk : if the bit check fails, the average time period for that check depends on the selected baud-rate range and on t clk . the baud-rate range is defined by baud 0 and baud 1 in the opmode register. if the bit check is ok, t bit-check depends on the number of bits to be checked (n bit-check ) and on the data rate used. depends on the result of the bit check t bit-check : extension factor defined by xsleepstd according to table 11-8 x sleep : off command yes no
13 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 8.3 configuring the bit check assuming a modulation scheme that contains two edges per bi t, two time frame checks verify one bit. this is valid for manchester, bi-phase, and most other modulation schemes. the ma ximum count of bits to be checked can be set to 0, 3, 6, or 9 bits using the variable n bit-check in the opmode register. this implies 0, 6, 12, and 18 edge-to-edge checks respectively. if n bit-check is set to a higher value, the receiver is less likely to sw itch to receiving mode due to noise. in the presence of a valid transmitter signal, the bit check takes less time if n bit-check is set to a lower value. in polling mode, the bit-check time is not dependent on nbit-check. figure 8-2 shows an example where three bits are te sted successfully and the data signal is transferred to pin data. figure 8-2. timing diagram for complete successful bit check according to figure 8-3 , the time window for the bit check is defined by tw o separate time limits. if the edge-to-edge time t ee is in between the lower bit-check limit t lim_min and the upper bit-check limit t lim_max , the check continues. if t ee is smaller than t lim_min or t ee exceeds t lim_max , the bit check is terminated and the receiver switches to sleep mode. figure 8-3. valid time window for bit check for best noise immunity using a low span between t lim_min and t lim_max is recommended. this is achieved using a fixed frequency at a 50% duty cycle for the tran smitter preburst. a ?11111...? or a ?10101 ...? sequence in manchester or bi-phase is suitable for this. a good compromise between receiver sensit ivity and susceptibility to noise is a time window of 30% regarding the expected edge-to-edge time t ee . using pre-burst patterns that contain various edge-to-edge time periods, the bit-check limits must be programmed according to the required span. the bit-check limits are determined by means of the formula below. t lim_min = lim_min t xclk t lim_max = (lim_max ? 1) t xclk lim_min and lim_max are defined by a 5-bi t word each within the limit register. using above formulas, lim_min and lim_max can be determined according to the required t lim_min , t lim_max and t xclk . the time resolution defining t lim_min and t lim_max is t xclk . the minimum edge-to-edge time t ee (t data_l_min , t data_h_min ) is defined according to the section 8.6 ?digital signal processing? on page 15 . the lower limit should be set to lim_min 10. the maximum value of the upper limit is lim_max = 63. if the calculated value for lim_min is < 19, it is recommended to check 6 or 9 bits (n bit-check ) to prevent switching to receiving mode due to noise. ic_active data_out (data) dem_out bit check t bit-check start-up mode (number of checked bits: 3) bit check ok 1/2 bit 1/2 bit 1/2 bit 1/2 bit 1/2 bit 1/2 bit start-check mode receiving mode t start-up 1/f sig t ee t lim_max t lim_min dem_out
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 14 figure 8-4 , figure 8-5 , and figure 8-6 illustrate the bit check for the bit-ch eck limits lim_min = 14 and lim_max = 24. when the ic is enabled, the signal processing circuits are enabled during t startup . the output of t he ask/fsk demodulator (dem_out) is undefined during that perio d. when the bit check becomes active, th e bit-check counter is clocked with the cycle t xclk . figure 8-4 shows how the bit check proceeds if the bit-check counte r value cv_lim is within the limits defined by lim_min and lim_max at the occurrence of a signal edge. in figure 8-5 the bit check fails as the value cv_lim is lower than the limit lim_min. the bit check also fails if cv_lim reaches lim_max. this is illustrated in figure 8-6 . figure 8-4. timing diag ram during bit check figure 8-5. timing diagram for failed bit check (condition: cv_lim < lim_min) figure 8-6. timing diagram for failed bit check (condition: cv_lim lim_max) ic_active bit-check counter dem_out bit check t bit-check start-up mode (lim_min = 14, lim_max = 24) bit check ok bit check ok 78 56 3 4 12 34 15 13 14 11 12 910 12 78 56 3 4 17 18 15 16 13 14 11 12 910 12 78 56 34 12 0 1/2 bit 1/2 bit 1/2 bit bit-check mode t start-up t xclk ic_active bit-check counter dem_out bit check t bit-check sleep mode 0 t sleep start-up mode (lim_min = 14, lim_max = 24) bit check failed (cv_lim_ < lim_min) 8 67 45 1112 910 23 1 56 34 12 0 1/2 bit bit-check mode t start-up ic_active bit-check counter dem_out bit check t bit-check sleep mode 0 t sleep start-up mode (lim_min = 14, lim_max = 24) bit check failed (cv_lim >= lim_max) 23 24 21 22 19 20 8 67 4 5 17 18 15 16 13 14 11 12 910 23 71 56 34 12 0 1/2 bit bit-check mode t start-up
15 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 8.4 duration of the bit check if no transmitter signal is pr esent during the bit check, the output of the ask/fsk demodulato r delivers random signals. the bit check is a statistical process and t bit-check varies for each check. therefore, an average value for t bit-check is given in the electrical characteristics. t bit-check depends on the selected baud-rate range and on t clk . a higher baud-rate range causes a lower value for t bit-check resulting in a lower current consumption in polling mode. in the presence of a valid transmitter signal, t bit-check is dependent on the frequency of that signal, f sig , and the count of the checked bits, n bit-check . a higher value for n bit-check thereby results in a longer period for t bit-check requiring a higher value for the transmitter pre-burst t preburst . 8.5 receiving mode if the bit check was successful for all bits specified by n bit-check , the receiver switches to receiving mode. according to figure 8-2 on page 13 , the internal data signal is switched to pin data in that case, and the data clock is available after the start bit has been detected (see figure 9-1 on page 18 ). a connected microcontroller can be woken up by the negative edge at pin data or by the data clock at pin data_clk. the receiver sta ys in that condition until it is switched back to polling mode explicitly. 8.6 digital signal processing the data from the ask/fsk demodulator (dem_out) is digitally processed in different ways and as a result converted into the output signal data. this pr ocessing depends on the selected baud-rate range (br_range). figure 8-7 illustrates how dem_out is synchronized by the extended clock cycle t xclk . this clock is also used for the bit-check counter. data can change its state only after t xclk has elapsed. the edge-to-edge time period t ee of the data signal as a result is always an integral multiple of t xclk . the minimum time period between two edges of the data signal is limited to t ee t data_min . this implies an efficient suppression of spikes at the da ta output. at the same time it limits the maximum frequency of edges at data. this eases the interrupt handling of a connected microcontroller. the maximum time period for data to stay low is limited to t data_l_max . this function is employed to ensure a finite response time in programming or switching off the receiver via pin data. t data_l_max is therefore longer than the maximum time period indicated by the transmitter data stream. figure 8-9 on page 16 gives an example where dem_out remains low after the receiver has sw itched to receiving mode. figure 8-7. synchronization of the demodulator output figure 8-8. debouncing of the demodulator output data_out (data) clock bit-check counter dem_out t xclk t ee data_out (data) dem_out t ee t ee t ee t data_min t data_min t data_min
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 16 figure 8-9. steady l state limited data output patte rn after transmission after the end of a data transmission, the receiver remains active. depending of the bit noise_disable in the opmode register, the output signal at pin data is high or random noise pulses appear at pin data (see section 10. ?digital noise suppression? on page 21 ). the edge-to-edge time period t ee of the majority of these noise pul ses is equal or slightly higher than t data_min . 8.7 switching the receiver back to sleep mode the receiver can be set back to polling m ode via pin data or via pin polling/_on. when using pin data, this pin must be pulled to lo w by the connected microcon troller for the period t1. figure 8-10 illustrates the timing of the off command (see figure 13-2 on page 28 ). the minimum value of t1 depends on the br_range. the maximum value for t1 is not limited; however, exceeding the specified value to prevent erasing the reset marker is not recommended. note also that an internal rese t for the opmode and the limit register is generated if t1 exceeds the specified values. this item is explained in more detail in the section 11. ?configuring the receiver? on page 23 . setting the receiver to sleep mode via data is achieved by progr amming bit 1 to ?1? during the register configuration. only one sync pulse (t3) is issued. the duration of the off command is determined by the sum of t1, t2, and t10. the sleep time t sleep elapses after the off command. note that the capacitive load at pin data is limited (see section 14. ?data interface? on page 30 ). figure 8-10. timing diagram of the off command using pin data ic_active data_out (data) dem_out bit check t data_l_max t data_min receiving mode start-up mode bit-check mode ic_active serial bi-directional data line out1 (microcontroller) data_out (data) t sleep t start-up t7 t4 t5 t3 t2 t1 t10 bit 1 ("1") (start bit) off-command x x receiving mode sleep mode start-up mode
17 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 figure 8-11. timing diagram of the off command using pin polling/_on figure 8-12. activating the receiving mode using pin polling/_on figure 8-11 ?timing diagram of the off command using pin pollin g/_on? illustrates how to se t the receiver back to polling mode using pin polling/_on. the pin polling/ _on must be held to low for the time period t on2 . after the positive edge on pin polling/_on and the delay t on3 , the polling mode is active and the sleep time t sleep elapses. using the polling/_on command is faster than using pin data ; however, this requires the use of an additional connection to the microcontroller. figure 8-12 ?activating the receiving mode usin g pin ?polling/_on? illustrates how to set the receiver to receiving mode using the pin polling/_on. the pin polling/_on must be held to low. after the delay t on1 , the receiver changes from sleep mode to start-up mode regardless of the programmed values for t sleep and n bit-check . as long as polling/_on is held to low, the values for t sleep and n bit-check is ignored, but not deleted (see section 10. ?digital noise suppression? on page 21 ). if the receiver is polled exclusively by a microcontroller, t sleep must be programmed to 31 (permanent sleep mode). in this case the receiver remains in sleep mode as long as polling/_on is held to high. ic_active polling/_on serial bi-directional data line data_out (data) t on2 t on3 receiving mode sleep mode start-up mode receiving mode bit-check mode bit check ok x x x x ic_active polling/_on serial bi-directional data line data_out (data) t on1 start-up mode sleep mode receiving mode x x
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 18 9. data clock the pin data_clk makes a data shift clock available to sample th e data stream into a shift regi ster. using this data clock, a microcontroller can easily synchronize the data stream. this clock can only be used for manchester and bi-phase coded signals. 9.1 generation of the data clock after a successful bit check, the receiver switches from polling mode to receiv ing mode and the data stream is available at pin data. in receiving mode, the data clock control logic (m anchester/bi-phase demodulator) is active and examines the incoming data stream. this is done, as with the bit check, by subsequent time frame checks where the distance between two edges is continuously compared to a prog rammable time window. as illustrated in figure 9-1 on page 18 , only two distances between two edges in manchester and bi-phase coded signals are valid (t and 2t). the limits for t are the same as used with the bit check. they can be programmed in the limit-register (lim_min and lim_max, see table 11-10 on page 26 and table 11-11 on page 26 ). the limits for 2t are calculated as follows: lower limit of 2t: lim_min_2t = (lim_min + lim_max) ? (lim_max ? lim_min)/2 upper limit of 2t: lim_max_2t= (lim_min + lim_max) + (lim_max ? lim_min)/2 (if the result for ?lim_min_2t? or ?lim_max_2t ? is not an integer value, it is rounded up.) the data clock is available, after the dat a clock control logic has detec ted the distance 2t (start bit) and is issued with the delay t delay after the edge on pin data (see figure 9-1 on page 18 ). if the data clock control logic detects a timing or logi cal error (manchester code violation), as illustrated in figure 9-2 on page 19 and figure 9-3 on page 19 , it stops the output of the data clock. the receiver remains in receiving mode and starts with the bit check. if the bit check was successf ul and the start bit has been detected, the data clock control logic starts again w ith the generation of the data clock (see figure 9-4 on page 19 ). use the function of the data clock only in conjunction with the bit check 3, 6 or 9 is recommended. if the bit check is set to 0 or the receiver is set to receiving mode using the pin polling/_o n, the data clock is available if the data clock control logic has detected the distan ce 2t (start bit). note that for bi-phase-coded signals, the dat a clock is issued at the end of the bit. figure 9-1. timing diagram of the data clock data_out (data) data_clk dem_out t delay '1' '1' '1' '0' '1' '0' '0' '1' 2t data preburst start bit bit-check mode receiving mode, data clock control logic active bit check ok t '1' '1' '1' t p_data_clk
19 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 figure 9-2. data clock disappears because of a timing error figure 9-3. data clock disappea rs because of a logical error figure 9-4. output of the data clock after a successful bit check the delay of the data clock is calculated as follows: t delay = t delay1 + t delay2 data_out (data) data_clk dem_out t ee t ee < t lim_min or t lim_max < t ee < t lim_min_2t or t ee > t lim_max_2t '1' '1' '1' '0' '1' '0' '0' '1' data receiving mode, data clock control logic active receiving mode, bit check active timing error '1' '1' '1' data_out (data) data_clk dem_out '1' '1' '1' '0' '1' '0' '1' '?' data receiving mode, data clock control logic active receiving mode, bit check active logical error (manchester code violation) '0' '0' '1' data_out (data) data_clk dem_out '1' '1' '1' '0' '1' '0' '0' '1' data bit check ok start bit receiving mode, data clock control logic active receiving mode, bit check active '1' '1' '1'
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 20 t delay1 is the delay between the internal signals da ta_out and data_in. fo r the rising edge, t delay1 depends on the capacitive load c l at pin data and the external pull-up resistor r pup . for the falling edge, t delay1 depends additionally on the external voltage v x (see figure 9-5 , figure 9-6 on page 20 and figure 13-2 on page 28 ). when the level of da ta_in is equal to the level of data_out, the data clock is issued after an additional delay t delay2 . note that the capacitive load at pin data is limited. if th e maximum tolerated capacitive load at pin data is exceeded, the data clock disappears (see section 14. ?data interface? on page 30 ). figure 9-5. timing characteristic of th e data clock (rising edge on pin data) figure 9-6. timing characteristic of the da ta clock (falling edge of the pin data) data_clk data_in serial bi-directional data line data_out v ii = 0.65 v s v ih = 0.65 v s v x t delay t p_data_clk t delay2 t delay1 data_clk data_in serial bi-directional data line data_out v ii = 0.35 v s v ih = 0.65 v s v x t delay t p_data_clk t delay2 t delay1
21 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 10. digital noise suppression after a data transmission, digital noise appears on the data output (see figure 10-1 ?output of digital noise at the end of the data stream?). to prevent digital noise keeping the connect ed microcontroller busy, it can be suppressed in two different ways: automatic noise suppression controlled noise suppression by the microcontroller 10.1 automatic noise suppression the receiver changes to bit-check mode at the end of a valid data stream if the bit noise_disable ( table 11-9 on page 25 ) in the opmode register is set to 1 (default). the digital noise is suppressed, and the level at pin data is high. the receiver changes back to receiving mode, if the bit check was successful. this method of noise suppression is recommended if the data stream is manchester or bi-phase coded and is active after power on. figure 10-3 ?occurrence of a pulse at the end of the data stream? ill ustrates the behavior of the data output at the end of a data stream. if the last period of the dat a stream is a high period (rising edge to fa lling edge), a pulse occurs on pin data. the length of the pulse depends on the selected baud-rate range. figure 10-1. output of digital nois e at the end of the data stream figure 10-2. automatic noise suppression data_clk data_out (data) data preburst receiving mode, data clock control logic active receiving mode, data clock control logic active bit-check mode bit check ok receiving mode, bit check active receiving mode, bit check active data digital noise digital noise digital noise preburst bit check ok data_clk data_out (data) data preburst receiving mode, data clock control logic active receiving mode, data clock control logic active bit-check mode bit-check mode bit-check mode bit check ok data preburst bit check ok
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 22 figure 10-3. occurrence of a pulse at the end of the data stream 10.2 controlled noise suppression by the microcontroller digital noise appears at the end of a valid data stream if the bit noise_disable (see table 11-9 on page 25 ) in the opmode register is set to 0. to suppress the noi se, the pin polling/_on must be set to low. the receiver remains in receiving mode. the off command then causes a change to start-up mode. the programmed sleep time (see table 11-7 on page 25 ) is not executed because the level at pin polling/_on is low; however, the bit c heck is active in this case. the off command also activates the bit check if the pin polling/_on is held to low. the receiver changes back to receiving mode if the bit check was successful. to activate the polling mode at the end of the data transmissi on, the pin polling/_on must be set to high. this way of suppressing the noise is recommen ded if the data stream is not manchester or bi-phase coded. figure 10-4. controlled noise suppression data_out (data) data_clk dem_out '1' '1' digital noise data stream receiving mode, data clock control logic active bit-check mode '1' t ee < t lim_min or t lim_max < t ee < t lim_min_2t or t ee > t lim_max_2t timing error t pulse t ee polling/_on (data_clk) serial bi-directional data line data preburst receiving mode receiving mode start-up mode sleep mode bit-check mode bit-check mode bit check ok data digital noise digital noise preburst off-command bit check ok
23 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 11. configuring the receiver the atmel ? ata8203/ata8204/ata8205 receiver is configured usi ng two 12-bit ram registers called opmode and limit. the registers can be programmed by means of the bidirectio nal data port. if the register content has changed due to a voltage drop, this condition is indicated by a the output pattern called reset marker (rm). if this occurs, the receiver must b e reprogrammed. after a power-on reset (por), the registers are set to default mode. if the receiver is operated in default mode, there is no need to program the registers. table 11-3 on page 23 shows the structure of the registers. according to table 11-1 , bit 1 defines whether the receiver is set back to polling mode using the off command (see ?receiving mode? on page 15 ) or whether it is programmed. bit 2 represents the register address. it selects the appropriate register to be programmed. for high programming reliability, bit 15 (stop bit), at the end of the programming operation, must be set to 0. table 11-1. effect of bit 1 and bi t 2 on programming the registers bit 1 bit 2 action 1 x the receiver is set back to polling mode (off command) 0 1 the opmode register is programmed 0 0 the limit register is programmed table 11-2. effect of bit 15 on programming the register bit 15 action 0 the values are written into th e register (opmode or limit) 1 the values are not written into the register table 11-3. effect of the configur ation words within the registers bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 off command 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? opmode register ? 0 1 br_range n bit-check modu- lation sleep x sleep noise suppression 0 baud1 baud0 bitchk1 bitchk0 ask/ _fsk sleep4 sleep3 sleep2 sleep1 sleep0 x sleepstd noise_ disable default values of bit 3...14 0 0 0 1 0 0 0 1 1 0 0 1 ? ? limit register ? 0 0 lim_min lim_max ? lim_ min5 lim_ min4 lim_ min3 lim_ min2 lim_ min1 lim_ min0 lim_ max5 lim_ max4 lim_ max3 lim_ max2 lim_ max1 lim_ max0 0 default values of bit 3...14 0 1 0 1 0 1 1 0 1 0 0 1 ?
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 24 the following tables illustrate the effect of the individual configuration words. th e default configuration is highlighted for each word. br_range sets the appropriate baud-rate range and simultaneous ly defines xlim. xlim is used to define the bit-check limits t lim_min and t lim_max as shown in table 11-10 on page 26 and table 11-11 on page 26 . table 11-4. effect of the configuration word br_range br_range baud-rate range/extension factor for bit-check limits (xlim) baud1 baud0 0 0 br_range0 (br_range0 = 1.0kbit/s to 1.8kbit/s) xlim = 8 (default) 0 1 br_range1 (br_range1 = 1.8kbit/s to 3.2kbit/s) xlim = 4 1 0 br_range2 (br_range2 = 3.2kbit/s to 5.6kbit/s) xlim = 2 1 1 br_range3 (br_range3 = 5.6kbit/s to 10kbit/s) xlim = 1 table 11-5. effect of the configuration word n bit-check n bit-check number of bits to be checked bitchk1 bitchk0 0 0 0 0 1 3 (default) 1 0 6 1 1 9 table 11-6. effect of the co nfiguration bit modulation modulation selected modulation ask/_fsk ? 0 fsk (default) 1 ask
25 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 table 11-7. effect of the configuration word sleep sleep start value for sleep counter (t sleep = sleep x sleep 1024 t clk ) sleep4 sleep3 sleep2 sleep1 sleep0 0 0 0 0 0 0 (receiver polls continuously until a valid signal occurs) 0 0 0 0 1 if x sleep = 1 t sleep = 2.11ms for f rf = 868.3mhz, t sleep = 2.12ms for f rf = 433.92mhz t sleep = 2.08ms for f rf = 315mhz 0 0 0 1 0 2 0 0 0 1 1 3 ... ... ... ... ... ... 0 0 1 1 0 if x sleep = 1 t sleep = 12.69ms for f rf = 868.3mhz, t sleep = 12.71ms for f rf = 433.92mhz t sleep = 12.52ms for f rf = 315mhz ... ... ... ... ... ... 1 1 1 0 1 29 1 1 1 1 0 30 1 1 1 1 1 31 (permanent sleep mode) table 11-8. effect of the configuration bit xsleep x sleep extension factor for sleep time (t sleep = sleep x sleep 1024 t clk) x sleepstd 0 1 (default) 1 8 table 11-9. effect of the configuration bit noise suppression noise suppression suppression of the digi tal noise at pin data noise_disable 0 noise suppression is inactive 1 noise suppression is active (default)
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 26 . table 11-10. effect of the configuration word lim_min lim_min (1) (lim_min < 10 is not applicable) lower limit value for bit check lim_min5 lim_min4 lim_min3 lim_min2 lim_min1 lim_min0 (t lim_min = lim_min xlim t clk ) 0 0 1 0 1 0 10 0 0 1 0 1 1 11 0 0 1 1 0 0 12 .. .. .. .. .. .. 0 1 0 1 0 1 21 (default, br_range0) (t lim_min = 347s for f rf = 868.3mhz t lim_min = 347s for f rf = 433.92mhz t lim_min = 342s for f rf = 315mhz) .. .. .. .. .. .. 1 1 1 1 0 1 61 1 1 1 1 1 0 62 1 1 1 1 1 1 63 note: 1. lim_min is also used to determine the margins of the data clock control logic (see section 9. ?data clock? on page 18 ). table 11-11. effect of the configuration word lim_max lim_max (1) (lim_max < 12 is not applicable) upper limit value for bit check lim_max5 lim_max4 lim_max3 lim_max2 lim_max1 lim_max0 (tlim_max = (lim_max ? 1) xlim t clk ) 0 0 1 1 0 0 12 0 0 1 1 0 1 13 0 0 1 1 1 0 14 .. .. .. .. .. .. 1 0 1 0 0 1 41 (default, br_range0) (t lim_max = 66s for f rf = 868.3mhz t lim_max = 662s for f rf = 433.92mhz t lim_max = 652s for f rf = 315mhz) .. .. .. .. .. .. 1 1 1 1 0 1 61 1 1 1 1 1 0 62 1 1 1 1 1 1 63 note: 1. lim_max is also used to determine the margins of the data clock control logic (see section 9. ?data clock? on page 18 ).
27 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 12. conservation of the register information the atmel ? ata8203/ata8204/ata8205 uses an integrated power-o n reset and brown-out detection circuitry as a mechanism to preserve the ram register information. according to figure 12-1 , a power-on reset (por) is generated if the supply voltage v s drops below the threshold voltage v threset . the default parameters are programmed in to the configuration registers in t hat condition. the por is cancelled after the minimum reset period t rst when v s exceeds v threset . a por is also generated when the supply voltage of the receiver is turned on. to indicate that condition, the receiver displays a reset marker (rm) at pin data after a reset. the rm is represented by the fixed frequency f rm at a 50% duty-cycle. rm can be cancelled using a low pu lse t1 at pin data. the rm has the following characteristics: f rm is lower than the lowest feasible frequency of a data signal. due to this, rm cannot be misinterpreted by the connected microcontroller. if the receiver is set back to polling mode using pin data, rm cannot be cancelled accidentally if t1 is applied as described in the proposal in section 13. ?programming the configuration register? on page 28 . using this conservation mechanism, the receiver cannot lose its register information without communicating this condition using the reset marker rm. figure 12-1. generation of the power-on reset por data_out (data) x t rst v threset v s 1/f rm
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 28 13. programming the c onfiguration register figure 13-1. timing of the register programming figure 13-2. data interface the configuration registers are se rially programmed using the bi-directional data line as shown in figure 13-1 and figure 13-2 . to start programming, the serial data line data is pulled to lo w by the microcontroller for the time period t1. when data has been released, the receiver becomes the master device . when the programming delay period t2 has elapsed, the receiver emits 15 subsequent synchronization pulses with the pul se length t3. after each of these pulses, a programming window occurs. the delay until the program wi ndow starts is determined by t4, the duration is defined by t5. the individual bits are set within the programming window. if the microcontroller pulls down pin data for the time period t7 during t5, the corresponding bit is set to ?0?. if no programming pulse t7 is issued, this bit is set to ?1?. all 15 bits are programmed this way. the time frame to program a bit is defined by t6. bit 15 is followed by the equivalent time window t9. during this window, the equivalence acknowledge pulse t8 (e_ack) occurs if the just programmed mode word is equivalent to th e mode word that was already stored in that register. e_ack should be used to verify that the mode word was correctly tr ansferred to the register. the register must be programmed twice in that case. a register can be programmed when the receiver is in both sleep-mode and active mode. during programming, the lna, lo, low-pass filter, if-amplifier, and the fsk/m sk demodulator are disabled. the t1 pulse is used to start the programming or to switch the receiver back to polling mode (off command). (the receiver is switched back to polling mode with the off command if bit 1 is set to ?1?.) the following convention shoul d be considered for the length of the programming start pulse t1: ic_active serial bi-directional data line out1 (microcontroller) data_out (data) t sleep t start-up t7 bit 2 ("1") (register select) bit 14 ("0") (poll 8) bit 15 ("0") (stop bit) bit 1 ("0") (start bit) programming frame x x receiving mode sleep mode start-up mode t6 t8 t4 t1 t2 t3 t5 t9 input interface data_out out1 (microcontroller) data_in i/o data v s = 4.5v to 5.5v v x = 5v to 20v r pup 0v/5v 0v to 20v microcontroller ata8203 ata8204 ata8205 serial bi-directional data line i d c l
29 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 using a t1 value of t1 (min) < t1 < 5632 tclk (where t1 (min) is the minimum specified value for the relevant br_range) when the receiver is active i. e., not in reset mode initiates the programming or off command. however, if this t1 value is used when the receiver is in reset mode, programming or of f command is not initiated a nd rm remains present at pin data. note, the rm cannot be deleted when using this t1 value. using a t1 value of t1 > 7936 tclk, programming or off command is initiated when the receiver is in both reset mode and active mode. the registers pmode and limit are set to the default values and the rm is deleted, if present. this t1 values can be used if the connected microcontroller detects an rm. additi onally, this t1 value can generally be used if the receiver operates in default mode. note that the capacitive load at pin data is limited.
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 30 14. data interface the data interface (see figure 13-2 on page 28 ) is designed for automotive requirement s. it can be connected using the pull- up resistor r pup up to 20v and is short-circuit-protected. the applicable pull-up resistor r pup depends on the load capacity c l at pin data and the selected br_range (see table 14-1 ). figure 14-1. application circuit: f rf = 315mhz (1) , 433.92mhz or 868mhz without saw filter note: for 315mhz application pin mode must be connected to gnd. table 14-1. applicable r pup - br_range applicable r pup c l 1nf b0 1.6k to 47k b1 1.6k to 22k b2 1.6 to 12k b3 1.6k to 5.6k c l 100pf b0 1.6k to 470k b1 1.6k to 220k b2 1.6k to 120k b3 1.6k to 56k table 14-2. input matching to 50 rf frequency (mhz) lna matching crystal frequency f xtal (mhz) c16 (pf) c17 (pf) l1 (nh) 315 not connected 3 39 14.71875 433.92 not connected 3 20 13.52875 868.3 1 3 6.8 13.55234 11 12 13 14 15 16 17 18 19 20 3 10 9 8 7 6 5 4 2 1 lnagnd lna_in lnaref agnd rssi test1 avcc cdem ic_active sens test2 test3 xtal1 xtal2 dvcc mode data_clk dgnd polling/_on data f crystal cl2 r2 l1 gnd c16 c17 rf_in vs r3 1.6k 56k to 150k cl1 data_clk sensitivity reduction polling/_on data c12 10nf 10% c13 10nf 10% c14 39nf 5% c7 4.7f 10% v x = 5v to 20v ic_active rssi ata8203 ata8204 ata8205 +
31 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 15. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters symbol min. max. unit supply voltage v s 6 v power dissipation p tot 1000 mw junction temperature t j 150 c storage temperature t stg ?55 +125 c ambient temperature t amb ?40 +85 c maximum input level, input matched to 50 p in_max 10 dbm 16. thermal resistance parameters symbol value unit junction ambient r thja 100 k/w
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 32 17. electrical characteristics atmel ata8203 all parameters refer to gnd, t amb = 25c, v s = 5v, f 0 = 315mhz unless otherwise specified. no. parameter test conditions symbol f rf = 315mhz 14.71875mhz oscillator variable oscillator unit type* min. typ. max. min. typ. max. min. typ. max. 1 basic clock cycle of the digital circuitry 1.1 basic clock cycle t clk 2.0382 2.0382 30/f xto 30/f xto s a 1.2 extended basic clock cycle br_range0 br_range1 br_range2 br_range3 t xclk 16.3057 8.1528 4.0764 2.0382 16.3057 8.1528 4.0764 2.0382 8 t clk 4 t clk 2 t clk 1 t clk 8 t clk 4 t clk 2 t clk 1 t clk s s s s a 2 polling mode 2.1 sleep time (see figure 8-1 , figure 8-10 and figure 13-1 ) sleep and xsleep are defined in the opmode register t sleep sleep x sleep 1024 2.0382 sleep x sleep 1024 2.0382 sleep x sleep 1024 t clk sleep x sleep 1024 t clk ms a 2.2 start-up time (see figure 8-1 and figure 8-4 ) br_range0 br_range1 br_range2 br_range3 t startup 1827 1044 1044 653 1827 1044 1044 653 896.5 512.5 512.5 320.5 t clk 896.5 512.5 512.5 320.5 t clk s s s s s a 2.3 time for bit check (see figure 8-1 average bit- check time while polling, no rf applied (see figure 8-5 and figure 8-6 ) br_range0 br_range1 br_range2 br_range3 t bit-check 0.45 0.24 0.14 0.08 0.45 0.24 0.14 0.08 ms ms ms ms c 2.4 time for bit check (see figure 8-1 bit-check time for a valid input signal f sig (see figure 8-5 ) n bit-check = 0 n bit-check = 3 n bit-check = 6 n bit-check = 9 t bit-check 1 t xclk 3/f sig 6/f sig 9/f sig 1 t xclk 3.5/f sig 6.5/f sig 9.5/f sig 1 t xclk 3/f sig 6/f sig 9/f sig 1 t clk 3.5/f sig 6.5/f sig 9.5/f sig ms ms ms ms c 3 receiving mode 3.1 intermediate frequency f if 987 f if = f lo /318 khz a 3.2 baud-rate range br_range0 br_range1 br_range2 br_range3 br_rang e 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 br_range0 2 s/t clk br_range1 2 s/t clk br_range2 2 s/t clk br_range3 2 s/t clk kbit/s kbit/s kbit/s kbit/s a *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
33 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 3.3 minimum time period between edges at pin data (see figure 4-2 and figure 8-8 , figure 8-9 ) (with the exception of parameter t pulse ) br_range = br_range0 br_range1 br_range2 br_range3 t data_min 163.06 81.53 40.76 20.38 163.06 81.53 40.76 20.38 10 t xclk 10 t xclk 10 t xclk 10 t xclk 10 t xclk 10 t xclk 10 t xclk 10 t xclk s s s s a 3.4 maximum low period at pin data (see figure 4-2 ) br_range = br_range0 br_range1 br_range2 br_range3 t data_l_max 2120 1060 530 265 2120 1060 530 265 130 t xclk 130 t xclk 130 t xclk 130 t xclk 130 t xclk 130 t xclk 130 t xclk 130 t xclk s s s s a 3.5 delay to activate the start-up mode (see figure 8-12 ) ton1 19.36 21.4 9.5 t clk 10.5 t clk s a 3.6 off command at pin polling/ _on (see figure 8-11 ) ton2 16.3 8 t clk s a 3.7 delay to activate the sleep mode (see figure 8-11 ) ton3 17.32 19.36 8.5 t clk 9.5 t clk s a 3.8 pulse on pin data at the end of a data stream (see figure 10-3 ) br_range = br_range0 br_range1 br_range2 br_range3 t pulse 16.3 8.15 4.07 2.04 16.3 8.15 4.07 2.04 8 t clk 4 t clk 2 t clk 1 t clk 8 t clk 4 t clk 2 t clk 1 t clk s s s s c 17. electrical characteristic s atmel ata8203 (continued) all parameters refer to gnd, t amb = 25c, v s = 5v, f 0 = 315mhz unless otherwise specified. no. parameter test conditions symbol f rf = 315mhz 14.71875mhz oscillator variable oscillator unit type* min. typ. max. min. typ. max. min. typ. max. *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 34 4 configuration of the receiver (see figure 12-1 and figure 13-1 ) 4.1 frequency of the reset marker frequency is stable within 50ms after por f rm 119.78 119.78 1/ (4096 t clk ) 1/ (4096 t clk ) hz a 4.2 programmin g start pulse br_range = br_range0 br_range1 br_range2 br_range3 after por t1 3310 2242 1708 1441 16175 11479 11479 11479 11479 1624 t clk 1100 t clk 838 t clk 707 t clk 7936 t clk 5632 t clk 5632 t clk 5632 t clk 5632 t clk s s s s s a 4.3 programmin g delay period t2 783 785 384.5 t clk 385.5 t clk s a 4.4 synchroniza - tion pulse t3 261 261 128 t clk 128 t clk s a 4.5 delay until of the program window starts t4 129 129 63.5 t clk 63.5 t clk s a 4.6 programmin g window t5 522 522 256 t clk 256 t clk s a 4.7 time frame of a bit t6 1044 1044 512 t clk 512 t clk s a 4.8 programmin g pulse t7 130.5 522 64 t clk 256 t clk s c 4.9 equivalent acknowledg e pulse: e_ack t8 261 261 128 t clk 128 t clk s a 4.10 equivalent time window t9 526 526 258 t clk 258 t clk s a 4.11 off-bit programmin g window t10 916 916 449.5 t clk 449.5 t clk s a 5 data clock (see figure 9-1 and figure 9-6 ) 5.1 minimum delay time between edge at data and data_clk br_range = br_range0 br_range1 br_range2 br_range3 t delay2 0 0 0 0 16.3057 8.1528 4.0764 2.0382 0 0 0 0 1 t xclk 1 t xclk 1 t xclk 1 t xclk s s s s c 5.2 pulse width of negative pulse at pin data_clk br_range = br_range0 br_range1 br_range2 br_range3 t p_data_clk 65.2 32.6 16.3 8.15 65.2 32.6 16.3 8.15 4 t xclk 4 t xclk 4 t xclk 4 t xclk 4 t xclk 4 t xclk 4 t xclk 4 t xclk s s s s a 17. electrical characteristic s atmel ata8203 (continued) all parameters refer to gnd, t amb = 25c, v s = 5v, f 0 = 315mhz unless otherwise specified. no. parameter test conditions symbol f rf = 315mhz 14.71875mhz oscillator variable oscillator unit type* min. typ. max. min. typ. max. min. typ. max. *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
35 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 18. electrical characterist ics atmel ata8204, ata8205 all parameters refer to gnd, t amb = 25c, v s = 5v, f 0 = 433.92mhz and f 0 = 868.3mhz unless otherwise specified. no. parameter test conditions symbol f rf = 433.92mhz 13.52875mhz oscillator f rf = 868.3mhz, 13.55234mhz oscillator variable oscillator unit type* min. typ. max. min. typ. max. min. typ. max. 6 basic clock cycle of the digital circuitry 6.1 basic clock cycle t clk 2.0696 2.0696 2.066 2.066 28/f xto 28/f xto s a 6.2 extended basic clock cycle br_range0 br_range1 br_range2 br_range3 t xclk 16.557 8.278 4.139 2.069 16.557 8.278 4.139 2.069 16.528 8.264 4.132 2.066 16.528 8.264 4.132 2.066 8 t clk 4 t clk 2 t clk 1 t clk 8 t clk 4 t clk 2 t clk 1 t clk s s s s a 7 polling mode 7.1 sleep time (see figure 8-1 , figure 8-10 and figure 13-1 ) sleep and xsleep are defined in the opmode register t sleep sleep x sleep 1024 2.0696 sleep x sleep 1024 2.0696 sleep x sleep 1024 2.066 sleep x sleep 1024 2.066 sleep x sleep 1024 t clk sleep x sleep 1024 t clk ms a 7.2 start-up time (see figure 8-1 and figure 8-4 ) br_range0 br_range1 br_range2 br_range3 t startup 1855 1060 1060 663 1855 1060 1060 663 1852 1058 1058 662 1852 1058 1058 662 896.5 512.5 512.5 320.5 t clk 896.5 512.5 512.5 320.5 t clk s s s s s a 7.3 time for bit check (see figure 8-1 average bit- check time while polling, no rf applied (see figure 8- 8 on page 15 and figure 8-9 on page 16 ) br_range0 br_range1 br_range2 br_range3 t bit-check 0.45 0.24 0.14 0.08 0.45 0.24 0.14 0.08 0.45 0.24 0.14 0.08 ms ms ms ms c 7.4 time for bit check (see figure 8-1 bit-check time for a valid input signal f sig (see figure 8- 5 on page 14 ) n bit-check = 0 n bit-check = 3 n bit-check = 6 n bit-check = 9 t bit-check 1 t xclk 3/f sig 6/f sig 9/f sig 1 t xclk 3.5/f sig 6.5/f sig 9.5/f sig 1 t xclk 3/f sig 6/f sig 9/f sig 1 t xclk 3.5/f sig 6.5/f sig 9.5/f sig 1 t xclk 3/f sig 6/f sig 9/f sig 1 t clk 3.5/f sig 6.5/f sig 9.5/f sig ms ms ms ms c 8 receiving mode 8.1 intermediate frequency f if 987 947.9 f if = f lo /438 for the 433.92mhz band (ata8204) f if = f lo /915 for the 868.3mhz band (ata8205) khz a 8.2 baud-rate range br_range0 br_range1 br_range2 br_range3 br_rang e 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 br_range0 2 s/t clk br_range1 2 s/t clk br_range2 2 s/t clk br_range3 2 s/t clk kbit/s kbit/s kbit/s kbit/s a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 36 8.3 minimum time period between edges at pin data (see figure 4-2 and figure 8-8 , figure 8-9 ) (with the exception of parameter t pulse ) br_range = br_range0 br_range1 br_range2 br_range3 t data_min 165.5 82.8 41.4 20.7 165.5 82.8 41.4 20.7 165.3 82.6 41.3 20.6 165.3 82.6 41.3 20.6 10 t xclk 10 t xclk 10 t xclk 10 t xclk 10 t xclk 10 t xclk 10 t xclk 10 t xclk s s s s a 8.4 maximum low period at pin data (see figure 4-2 ) br_range = br_range0 br_range1 br_range2 br_range3 t data_l_max 2152 1076 538 269 2152 1076 538 269 2148 1074 537 268.5 2148 1074 537 268.5 130 t xclk 130 t xclk 130 t xclk 130 t xclk 130 t xclk 130 t xclk 130 t xclk 130 t xclk s s s s a 8.5 delay to activate the start-up mode (see figure 8-12 ) ton1 19.6 21.7 19.6 21.7 9.5 t clk 10.5 t clk s a 8.6 off command at pin polling/ _on (see figure 8-11 ) ton2 16.5 16.5 8 t clk s a 8.7 delay to activate the sleep mode (see figure 8-11 ) ton3 17.6 19.6 17.6 19.6 8.5 t clk 9.5 t clk s a 8.8 pulse on pin data at the end of a data stream (see figure 10-3 ) br_range = br_range0 br_range1 br_range2 br_range3 t pulse 16.557 8.278 4.139 2.069 16.557 8.278 4.139 2.069 16.528 8.264 4.132 2.066 16.528 8.264 4.132 2.066 8 t clk 4 t clk 2 t clk 1 t clk 8 t clk 4 t clk 2 t clk 1 t clk s s s s c 18. electrical characteristics at mel ata8204, ata8205 (continued) all parameters refer to gnd, t amb = 25c, v s = 5v, f 0 = 433.92mhz and f 0 = 868.3mhz unless otherwise specified. no. parameter test conditions symbol f rf = 433.92mhz 13.52875mhz oscillator f rf = 868.3mhz, 13.55234mhz oscillator variable oscillator unit type* min. typ. max. min. typ. max. min. typ. max. *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
37 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 9 configuration of the receiver (see figure 12-1 and figure 13-1 ) 9.1 frequency of the reset marker frequency is stable within 50ms after por f rm 117.9 117.9 118.2 118.2 1/ (4096 t clk ) 1/ (4096 t clk ) hz a 9.2 program- ming start pulse br_range = br_range0 br_range1 br_range2 br_range3 after por t1 3361 2276 1734 1463 16425 11656 11656 11656 11656 3355 2272 1731 1460 11636 11636 11636 11636 1624 t clk 1100 t clk 838 t clk 707 t clk 7936 t clk 5632 t clk 5632 t clk 5632 t clk 5632 t clk s s s s s a 9.3 programmin g delay period t2 796 798 794 796 384.5 t clk 385.5 t clk s a 9.4 synchroniza- tion pulse t3 265 265 264 264 128 t clk 128 t clk s a 9.5 delay until of the program window starts t4 131 131 131 131 63.5 t clk 63.5 t clk s a 9.6 programmin g window t5 530 530 529 529 256 t clk 256 t clk s a 9.7 time frame of a bit t6 1060 1060 1058 1058 512 t clk 512 t clk s a 9.8 programmin g pulse t7 132 530 132 529 64 t clk 256 t clk s c 9.9 equivalent acknowledge pulse: e_ack t8 265 265 264 264 128 t clk 128 t clk s a 9.10 equivalent time window t9 534 534 533 533 258 t clk 258 t clk s a 9.11 off-bit programmin g window t10 930 930 929 929 449.5 t clk 449.5 t clk s a 10 data clock (see figure 9-1 and figure 9-6 ) 10.1 minimum delay time between edge at data and data_clk br_range = br_range0 br_range1 br_range2 br_range3 t delay2 0 0 0 0 16.557 8.278 4.139 2.069 0 0 0 0 16.528 8.264 4.132 2.066 0 0 0 0 1 t xclk 1 t xclk 1 t xclk 1 t xclk s s s s c 10.2 pulse width of negative pulse at pin data_clk br_range = br_range0 br_range1 br_range2 br_range3 t p_data_clk 66.2 33.1 16.5 8.3 62.2 33.1 16.5 8.3 66.1 33.0 16.5 8.25 66.1 33.0 16.5 8.25 4 t xclk 4 t xclk 4 t xclk 4 t xclk 4 t xclk 4 t xclk 4 t xclk 4 t xclk s s s s a 18. electrical characteristics at mel ata8204, ata8205 (continued) all parameters refer to gnd, t amb = 25c, v s = 5v, f 0 = 433.92mhz and f 0 = 868.3mhz unless otherwise specified. no. parameter test conditions symbol f rf = 433.92mhz 13.52875mhz oscillator f rf = 868.3mhz, 13.55234mhz oscillator variable oscillator unit type* min. typ. max. min. typ. max. min. typ. max. *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 38 19. electrical characteristics atmel ata8203, ata8204, ata8205 all parameters refer to gnd, t amb = 25c, v s = 5v, f 0 = 868.3mhz, f 0 = 433.92mhz and f 0 = 315mhz, unless otherwise specified. no. parameters test conditions symbol min. typ. max. unit type* 11 current consumption 11.1 current consumption sleep mode (xto and polling logic active) is off 170 290 a a ic active (start-up-, bit-check-, receiving mode) pin data = h fsk ask is on 8.5 8.0 11.0 10.4 ma ma a 12 lna, mixer, polyphase low-pass and if amplifier (input matched according to figure 14-1 on page 30 referred to rfin) 12.1 third-order intercept point lna/mixer/if amplifier 868mhz 433mhz 315mhz iip3 ?18 ?23 ?24 dbm c 12.2 lo spurious emission required according to i-ets 300220 is lorf ?70 ?57 dbm a 12.3 system noise figure with power matching |s11| < ?10db nf 5 db b 12.4 lna_in input impedance at 868.3mhz at 433.92mhz at 315mhz zi lna_in (14.15 ? j73.53) (19.3 ? j113.3) (26.97 ? j158.7) c 12.5 1 db compression point at 868.3mhz at 433.92mhz at 315mhz ip 1db ?27.7 ?32.7 ?33.7 dbm c 12.6 image rejection within the complete image band 20 30 db a 12.7 maximum input level ber 10 -3 , fsk mode ask mode p in_max ?10 ?10 dbm dbm c 13 local oscillator 13.1 operating frequency range vco ata8205 ata8204 ata8203 f vco 868 431.5 312.5 870 436.5 317.5 mhz mhz mhz a 13.2 phase noise local oscillator f osc = 868.3mhz at 10mhz f osc = 433.92mhz at 10mhz f osc = 315mhz at 10mhz l (fm) ?140 ?143 ?143 ?130 ?133 ?133 dbc/hz b 13.3 spurious of the vco at f xto ?55 ?45 dbc b 13.4 xto pulling xto pulling, appropriate load capacitance must be connected to xtal, crystal cl1 and cl2 f xtal = 14.71875mhz (315mhz band) f xtal = 13.52875mhz (433mhz band) f xtal = 13.55234mhz (868mhz band) f xto ?10ppm f xtal +10ppm mhz b 13.5 series resonance resistor of the crystal parameter of the supplied crystal r s 120 b *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
39 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 13.6 static capacitance at pin xtal1 to gnd parameter of the supplied crystal and board parasitics c l1 ?5% 18 +5% pf b 13.7 static capacitance at pin xtal2 to gnd parameter of the supplied crystal and board parasitics c l2 ?5% 18 +5% pf b 13.8 crystal series resistor rm at start-up c 0 < 1.8pf, c l = 9pf f xtal = 14.71875mhz 1.5 k b c 0 < 2.0pf, c l = 9pf f xtal = 13.52875mhz f xtal = 13.55234mhz 1.5 k b 14 analog signal processing (input matched according to figure 14-1 on page 30 referred to rfin) 14.1 input sensitivity ask 300 khz if filter (ata8203/ata8204) ask (level of carrier) ber 10 -3 , 100% mod f in = 315mhz/433.92mhz v s = 5v, t amb = 25c f if = 987khz p ref_ask br_range0 ?111 ?113 ?115 dbm b br_range1 ?109.5 ?111.5 ?113.5 dbm b br_range2 ?109 ?111 ?113 dbm b br_range3 ?107 ?109 ?111 dbm b 14.2 input sensitivity ask 600 khz if filter (ata8205) ask (level of carrier) ber 10 -3 , 100% mod f in = 868.3mhz v s = 5v, t amb = 25c f if = 948khz p ref_ask br_range0 ?109 ?111 ?113 dbm b br_range1 ?107.5 ?109.5 ?111.5 dbm b br_range2 ?107 ?109 ?111 dbm b br_range3 ?105 ?107 ?109 dbm b 14.3 sensitivity variation ask for the full operating range compared to t amb =25c, v s =5v (ata8203/ata8204/ata8205 ) 300khz and 600khz f in = 315mhz/433.92mhz/868.3mhz p ask = p ref_ask + p ref p ref +2.5 ?1.5 db b 14.4 sensitivity variation ask for full operating range including if filter compared to t amb = 25c, v s = 5v 300 khz version (ata8203/ata8204) f in = 315mhz/433.92mhz f if = 987khz f if = ?110khz to +110khz f if = ?140khz to +140khz p ask = p ref_ask + p ref p ref +7.5 +9.5 ?1.5 ?1.5 db db b 600khz version (ata8205) f in = 868.3mhz f if = 948khz f if = ?210khz to +210khz f if = ?270khz to +270khz p ask = p ref_ask + p ref p ref +6.5 +8.5 ?1.5 ?1.5 db db b 19. electrical characteristics atmel ata8203, ata8204, ata8205 (continued) all parameters refer to gnd, t amb = 25c, v s = 5v, f 0 = 868.3mhz, f 0 = 433.92mhz and f 0 = 315mhz, unless otherwise specified. no. parameters test conditions symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 40 14.5 input sensitivity fsk 300khz if filter (ata8203/ata8204) ber 10 -3 f in = 315mhz/433.92mhz v s = 5v, t amb = 25c f if = 987khz br_range0 df = 16khz df = 10khz to 30khz p ref_fsk ?104 ?102 ?107 ?108.5 ?108.5 dbm dbm b br_range1 df = 16khz df = 10khz to 30khz p ref_fsk ?102 ?100 ?105 ?106.5 ?106.5 dbm dbm b br_range2 df = 16khz df = 10khz to 30khz p ref_fsk ?100.5 ?98.5 ?103.5 ?105 ?105 dbm dbm b br_range3 df = 16khz df = 10khz to 30khz p ref_fsk ?98.5 ?96.5 ?101.5 ?103 ?103 dbm dbm b 14.6 input sensitivity fsk 600khz if filter (ata8205) ber 10 -3 f in = 868.3mhz v s = 5v, t amb = 25c f if = 948khz br_range0 df = 16khz to 28khz df = 10khz to 100khz p ref_fsk ?102 ?100 ?105 ?106.5 ?106.5 dbm dbm b br_range1 df = 16khz 28khz df = 10khz to 100khz p ref_fsk ?100 ?98 ?103 ?104.5 ?104.5 dbm dbm b br_range2 df = 18khz 31khz df = 13khz to 100khz p ref_fsk ?98.5 ?96.5 ?101.5 ?103 ?103 dbm dbm b br_range3 df = 25khz 44khz df = 20khz to 100khz p ref_fsk ?96.5 ?94.5 ?99.5 ?101 ?101 dbm dbm b 14.7 sensitivity variation fsk for the full operating range compared to t amb =25c, v s =5v (ata8203/ata8204/ata8205 ) 300khz and 600khz versions f in = 315mhz/433.92mhz/868.3mhz p fsk = p ref_fsk + p ref p ref +3 ?1.5 db b 19. electrical characteristics atmel ata8203, ata8204, ata8205 (continued) all parameters refer to gnd, t amb = 25c, v s = 5v, f 0 = 868.3mhz, f 0 = 433.92mhz and f 0 = 315mhz, unless otherwise specified. no. parameters test conditions symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
41 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 14.8 sensitivity variation fsk for the full operating range including if filter compared to t amb = 25c, v s = 5v 300khz version (ata8203/ata8204) f in = 315mhz/433.92mhz f if = 987khz f if = ?110khz to +110khz f if = ?140khz to +140khz f if = ?180khz to +180khz p fsk = p ref_fsk + p ref p ref +8 +10 +13 ?2 ?2 ?2 db db db b 600khz version (ata8205) f in = 868.3mhz f if = 948khz f if = ?150khz to +150khz f if = ?200khz to +200khz f if = ?260khz to +150khz p fsk = p ref_fsk + p ref p ref +7 +9 +12 ?2 ?2 ?2 db db db b 14.9 s/n ratio to suppress in-band noise signals. noise signals may have any modulation scheme ask mode fsk mode snr ask snr fsk 10 2 12 3 db db c 14.10 dynamic range rssi amplifier r rssi 60 db a 14.11 rssi output voltage range v rssi 1 3.5 v a 14.12 rssi gain g rssi 20 mv/db a 14.13 lower cut-off frequency of the data filter cdem = 33nf fcu_df 0.11 0.16 0.20 khz b 14.14 recommended cdem for best performance br_range0 (default) br_range1 br_range2 br_range3 cdem 39 22 12 8.2 nf nf nf nf c 14.15 edge-to-edge time period of the input data signal for full sensitivity br_range0 (default) br_range1 br_range2 br_range3 t ee_sig 270 156 89 50 1000 560 320 180 ms ms ms ms c 14.16 upper cut-off frequency data filter upper cut-off frequency programmable in 4 ranges using a serial mode word br_range0 (default) br_range1 br_range2 br_range3 fu 2.8 4.8 8.0 15.0 3.4 6.0 10.0 19.0 4.0 7.2 12.0 23.0 khz khz khz khz b 14.17 reduced sensitivity 300khz version (ata8203/ata8204) r sense connected from pin sens to v s , input matched according to figure 14-1 ?application circuit, f in = 315mhz/433.92mhz, v s = 5v, t amb = +25c dbm (peak level) r sense = 56k p ref_red ?71 ?79 ?86 dbm b r sense = 100k p ref_red ?80 ?88 ?96 dbm b 19. electrical characteristics atmel ata8203, ata8204, ata8205 (continued) all parameters refer to gnd, t amb = 25c, v s = 5v, f 0 = 868.3mhz, f 0 = 433.92mhz and f 0 = 315mhz, unless otherwise specified. no. parameters test conditions symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter f cu_df 1 2 30 k cdem --------------------------------------------------------- - =
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 42 14.18 reduced sensitivity 600khz version (ata8205) r sense connected from pin sens to v s , input matched according to figure 14-1 ?application circuit, f in = 868.3mhz, v s = 5v, t amb = +25c dbm (peak level) r sense = 56k p ref_red ?60 ?68 ?76 dbm b r sense = 100k p ref_red ?69 ?77 ?85 dbm b 14.19 reduced sensitivity variation over full operating range r sense = 56k r sense = 100k p red = p ref_red + p red p red 5 5 0 0 0 0 db db c 14.20 reduced sensitivity variation for different values of r sense values relative to r sense = 56k r sense = 56k r sense = 68k r sense = 82k r sense = 100k p red 0 ?3.5 ?6.0 ?9.0 db db db db c 14.21 threshold voltage for reset v threset 1.95 2.8 3.75 v a 15 digital ports 15.1 data output - saturation voltage low - max voltage at pin data - quiescent current - short-circuit current - ambient temp. in case of permanent short-circuit data input - input voltage low - input voltage high i ol 12ma i ol = 2ma v oh = 20v v ol = 0.8v to 20v v oh = 0v to 20v v ol v ol v oh i qu i ol_lim t amb_sc v il v ich 13 0.65 v s 0.35 0.08 30 0.8 0.3 20 20 45 85 0.35 v s v v v a ma c v v a 15.2 data_clk output - saturation voltage low - saturation voltage high idata_clk = 1ma idata_clk = ?1ma v ol v oh v s ? 0.4v 0.1 v s ? 0.15v 0.4 v v a 15.3 ic_active output - saturation voltage low - saturation voltage high iic_active = 1ma iic_active = ?1ma v ol v oh v s ? 0.4 v 0.1 v s ? 0.15v 0.4 v v a 15.4 polling/_on input - low level input voltage - high level input voltage receiving mode polling mode v il v ih 0.8 v s 0.2 v s v v a 15.5 mode pin - high level input voltage test input must always be set to high v ih 0.8 v s v a 15.6 test 1 pin - low level input voltage test input must always be set to low v il 0.2 v s v a 19. electrical characteristics atmel ata8203, ata8204, ata8205 (continued) all parameters refer to gnd, t amb = 25c, v s = 5v, f 0 = 868.3mhz, f 0 = 433.92mhz and f 0 = 315mhz, unless otherwise specified. no. parameters test conditions symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
43 ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 21. package information 20. ordering information extended type number package remarks ata8203p3c-tkqw sso20 315mhz version, moq 4000 ata8204p3c-tkqw sso20 433mhz version, moq 4000 ata8205p6c-tkqw sso20 868mhz version, moq 4000 package drawing contact: packagedrawings@atmel.com gpc drawing no. rev. title 6.543-5182.01-4 1 04/16/14 package: sso20 4.4mm common dimensions (unit of measure = mm) min nom note max symbol dimensions in mm specifications according to din technical drawings 0.1 0.15 0.05 a1 4.4 4.5 4.3 e1 0.25 0.3 0.2 b 0.65 bsc e 0.15 0.2 0.1 c 0.6 0.7 0.5 l 6.4 6.5 6.3 e 6.5 6.6 6.4 d 0.9 0.95 0.85 a2 1.0 1.1 0.9 a 20 11 110 d b e a a1 a2 c e1 e l
ata8203/ata8204/ata8205 [datasheet] 9121d?indco?09/14 44 22. revision history please note that the following page numbers re ferred to in this section re fer to the specific revision mentioned, not to this document. revision no. history 9121d-indco-09/14 ? section 20 ?ordering information? on page 44 updated ? section 21 ?package information? on page 44 updated 9121c-indco-12/12 ? section 20 ?ordering information? on page 43 changed 9121b-indco-04/09 ? figure 1-1 ?system block diagram? on page 2 changed
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